1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication, and in particular to lithography patterning of thin film stacks for lithography using light having a wavelength of 193 nm or less.
2. Discussion of Related Art
Present semiconductor fabrication techniques may be used to generate single electrode transistor gates using 193 nm wavelength lithography technology or dual electrode flash memory transistor gates using 248 nm wavelength lithography technology.
FIG. 1 illustrates a flash memory transistor gate stack. The flash memory gate stack is formed on substrate 100. The gate stack of the flash memory transistor consists of a control gate electrode layer 108 deposited over an inter-electrode dielectric 106, over a floating gate layer 104, over the gate dielectric 102, on a substrate 100. Source/drain spacer liner dielectric 140 is formed on either side of the flash memory gate stack. Source/drain spacer dielectric 142 is formed on either side of the gate stack on top of the source/drain spacer liner dielectric 140.
FIG. 2 illustrates the flash memory gate stack after the resist has been patterned using light 280 having a wavelength of 248 nm or greater. The thickness of the resist 214 is bounded by etch resistance and patterning resolution. The flash transistor gate is etched using a Self-Aligned MOS (SAMOS) process. The SAMOS process allows all layers of the flash transistor gate stack to be etched using the resist as a mask, including the gate dielectric 202, the floating gate electrode 204, the interelectrode dielectric 206, and the control gate electrode 208.
To achieve high resolution patterning with 193 nm (or less) lithography for flash transistors, a change in resist formulation is required. The resist formulation for 193 nm lithography compromises the ability of the resist to withstand the environment required to etch the SAMOS flash gate stack, and is not stable in etch chemistries. Thus, it is undesirable to use resist as a mask to etch the flash SAMOS gate stack using 193 nm or less lithography.
Hardmask materials that consist of similar elements to those found in the inter-poly dielectric layer, such as a nitride layer, are also undesirable for use as a SAMOS mask. These materials may be compromised during the etch process. Furthermore, the removal of a hardmask consisting of a similar material as the inter-poly dielectric layer may compromise the dielectric and lead to device failure.